1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method for a semiconductor memory device, and, more particularly to a semiconductor memory device and a manufacturing method for a semiconductor memory device preferably applied to a magnetic random access memory (MRAM) in which a magnetoresistive element that magnetically stores information therein is deposited on a selection transistor.
2. Description of the Related Art
The MRAM is attracting attention as a semiconductor memory device having high-speed accessibility similar to that of a static RAM (SRAM), a high degree of integration similar to that of a dynamic RAM (DRAM), and nonvolatility similar to that of a flash memory.
The MRAM includes magnetoresistive elements that magnetically store therein information, and a selection transistor that selects a magnetoresistive element of a unit cell for which reading or writing is performed. A gate electrode of the selection transistor is placed on a semiconductor substrate, and a source and a drain thereof are formed on the semiconductor substrate on both sides of the gate electrode. The magnetoresistive element is placed on a multilayer interconnection layer formed on the selection transistor.
A conventional technique discloses a method of forming a magnetic memory element that has a data storing function utilizing a magnetic body on a vertical transistor, and arranging a bit line connected to the vertical transistor via the magnetic memory element and a writing word line crossing over the bit line, to increase the degree of integration in the MRAM (see Japanese Patent Application Laid-open No. 2003-218328, for example).
However, in the method disclosed in Japanese Patent Application Laid-open No. 2003-218328, because both sides of an impurity deposition are coated with a gate deposition, a shielding effectiveness of flux generated by a current that passes through the impurity deposition is not sufficiently high. Accordingly, when the degree of integration in the MRAM is increased, magnetic interference between memory cells becomes larger and the risk of malfunctions becomes higher.
Further, in the method disclosed in Japanese Patent Application Laid-open No. 2003-218328, the writing word line needs to be arranged over the bit line separately from a word line as the gate deposition. Therefore, the number of interconnections is increased, which hinders an increase in the degree of integration in the MRAM.